1. Field of the Invention
The present invention is related to a voltage hold circuit, and more particularly, to a voltage hold circuit of a delay-locked loop circuit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a block diagram illustrating a prior art delay-locked loop (DLL) circuit 10. The DLL circuit 10 is configured to generate output signals having the same cycle length as the input clock signals, but delayed by a cycle. The DLL circuit 10 includes a phase frequency detector 11, a charge pump circuit 12, a capacitor 13, a voltage controlled delay line (VCDL) 14 and a dummy delay circuit 15. The phase frequency detector 11 is configured to receive input clock signals SI and feedback signals FB, thereby generating UP signals SU and DOWN signals SD according to phase difference and frequency difference between the two detected signals. The charge pump circuit 12 is configured to receive the UP signals SU and the DOWN signals SD, thereby changing the generated current signals according to the logic state of the UP signals SU and the DOWN signals SD. The capacitor 13 is configured to receive the current signals from the charge pump circuit 12, thereby generating a DC voltage VA by low pass filtering the current signals. The voltage controlled delay line 14 is configured to receive the input clock signals SI and the DC voltage VA, thereby determining the required delay time of the input clock signals SI according to the DC voltage VA. Feedback signal FB is generated as the output signal SO of the VCDL 14 passes through the dummy delay circuit 14.
For the DLL circuit with a feedback loop, a node voltage VA (such as 736 mV) raises/decreases to voltage VDD/VSS due to partial power shutdown and leakage current of components in the feedback loop. After that, it takes a lot of time for the node voltage VA to be reestablished to the original voltage (736 mV) so as to recover the feedback loop. However, a common double data rate dynamic random access memory (DDR DRAM) chip regains normal operation about 2 to 10 time clock cycles after leaving partial power saving mode. Therefore, it is important to maintain the level of the node voltage VA. Maintaining the feedback loop in the power saving mode consumes a lot of power. Maintain the node voltage VA using analog-to-digital converter (ADC) or digital-to-analog converter (DAC) occupies large chip space, while using large capacitor results in large loading effect. Besides, leakage current of switch components is an issue which needs to be taken into consideration.